The present invention relates to an insulated gate field effect transistor (which will be herein referred to as a xe2x80x9cIGFETxe2x80x9d) and a semiconductor device using the IGFET.
FIGS. 8A and 8B are cross-sectional and plan views illustrating the structure of a known IGFET, respectively. FIG. 8A illustrates a cross section of the known IGFET taken along the line Xxe2x80x94X of FIG. 8B.
As shown in FIGS. 8A and 8B, the known IGFET 500 is formed using an SOI substrate and includes a semiconductor layer 51, a buried insulating film 52, and a semiconductor layer 53 serving as an active region. Furthermore, a trench 52t is provided so as to surround the semiconductor layer 53, and the trench 52t is filled with an insulating film, thereby forming an isolation region 54. On a region of the semiconductor layer 53 which is to be a channel, formed are a gate insulating film 55 and a gate electrode 56 in this order. A gate sidewall spacer 57 is then formed so as to surround the gate electrode 56. Furthermore, an interlevel insulating film 58 is formed on the substrate and then a contact 59 is formed so as to be connected to the gate electrode 56 through the interlevel insulating film 58. The gate width W1 of the semiconductor layer 53 is about 1 xcexcm. The interlevel insulating film 58 is not shown in FIG. 8B.
Next, a method for fabricating the known IGFET 500 will be described with reference to FIGS. 9A through 9D. FIGS. 9A through 9D are cross-sectional views illustrating respective process steps for fabricating the known IGEFT 500.
First, in the process step shown in FIG. 9A, an SOI substrate including a semiconductor layer 51, a buried insulating film 52 and a semiconductor layer 53 is prepared. Next, a multilayer film including a silicon oxide film 60 and a silicon nitride film 61 is formed on the SOI substrate and the multilayer film is patterned. Etching is then performed using the patterned multilayer film as a mask to obtain the semiconductor layer 53 serving as an active region and a trench 52t to which part of the buried insulating film 52 is exposed.
Next, in the process step shown in FIG. 9B, side parts of the semiconductor layer 53 are subjected to preliminary oxidation, thereby forming a side oxide film 62 (having a thickness of about 10 to 30 nm) on the side parts of the semiconductor layer 53. During the preliminary oxidation, an oxidizing agent enters into the interface between the buried insulating film 52 and the semiconductor layer 53 to oxidize the bottom part of the semiconductor layer 53 simultaneously with the side parts of the semiconductor layer 53. As a result, a birds"" beak-shaped bottom oxide film 62a is formed. With the bottom oxide film 62a, the peripheral portion of the semiconductor layer 53 is lifted as shown in FIG. 9B, and therefore, the semiconductor layer 53 has a shape in which a depression is made in the center portion thereof (which will be herein referred to as a xe2x80x9cwing shapexe2x80x9d).
Next, in the process step shown in FIG. 9C, an oxide film is deposited using CVD on the part of the buried insulating film 52 which is exposed to the trench 52t. Subsequently, the upper surface of the substrate is planarized by CMP, and an isolation region 54 is formed. Next, a gate insulating film 55 and a gate electrode 56 are formed and then a gate sidewall spacer 57 is formed. Thereafter, ions of an impurity are implanted using the gate electrode 56 and the gate sidewall spacer 57 as a mask, thereby forming source/drain regions (not shown in FIG. 9C).
Next, in the process step shown in FIG. 9D, an interlevel insulating film 58 is formed by CVD and then a contact 59 is formed so as to pass through the interlevel insulating film 58 and reach the gate electrode 56.
In the above method for fabricating an IGFET 500, the peripheral portion of the semiconductor layer 53 is lifted, so that the semiconductor layer 53 becomes to have a wing shape as shown in FIG. 9B. This lift is caused by the fact that the gate width W1 of the semiconductor layer 53 is about 1 xcexcm whereas the bottom oxide film 62a formed by thermal oxidation extends inwardly from each edge of the semiconductor layer 53 only by a distance of about 0.3 xcexcm. As a result, a crystal strain occurs in the peripheral portion of the semiconductor layer 53 serving as an active region, thus resulting in crystal defects or abnormal diffusion of a dopant impurity in the semiconductor layer 53.
In an IGFET, therefore, leakage of a dopant impurity between the drain and the source due to abnormal diffusion of the dopant impurity of the source region and the drain region, junction leakage between the drain and the substrate, or the like easily occurs. Such leakage causes high fraction defective in the IGFET, resulting in a remarkable reduction in the yield of a semiconductor device using the IGFET.
The present invention has been devised in order to solve the above-described problems, and it is therefore an object of the present invention to provide a semiconductor device of low fraction defective.
A semiconductor device in accordance with the present invention includes: an insulating layer; a semiconductor region formed on the insulating layer; a trench that surrounds side parts of the semiconductor region and reaches the insulating layer; an isolation insulating film formed in the trench; a semiconductor element in which the semiconductor region serves as an active region; a side oxide film formed by oxidizing the side parts of the semiconductor region and located between the rest of the semiconductor region and the isolation insulating film; and a bottom oxide film that is formed by oxidizing a bottom part of the semiconductor region, is located over the entire interface between the rest of the semiconductor region and the insulating layer, and has side surfaces reaching the side oxide film.
As described above, the semiconductor device of the present invention includes a bottom oxide film that is formed by oxidizing a bottom part of the semiconductor region, is located over the entire interface between the rest of the semiconductor region and the insulating layer, and has side surfaces reaching the side oxide film. This suppressed the occurrence of crystal defects or abnormal diffusion of a dopant impurity in the semiconductor region. Therefore, in the semiconductor element in which the semiconductor region serves as an active region, the occurrence of crystal defects or abnormal diffusion of a dopant impurity can be suppressed.
The semiconductor element may be a FET including a gate insulating film formed on the semiconductor region, a gate electrode formed on the gate insulating film, and source/drain regions formed on both sides of the gate electrode.
The semiconductor region preferably has a length of 0.5 xcexcm or less in the gate width direction.
Another semiconductor device in accordance with the present invention includes: an insulating layer; a semiconductor region formed on the insulating layer; a trench that surrounds side parts of the semiconductor region and reaches the insulating layer; an isolation insulating film formed in the trench; a gate insulating film formed on the semiconductor region; a gate electrode formed on the gate insulating film; a side oxide film formed by oxidizing the side parts of the semiconductor region and located between the rest of the semiconductor region and the isolation insulating film; and a bottom oxide film that is formed by oxidizing a peripheral portion of a bottom part of the semiconductor region, is located under the peripheral portion of the rest of semiconductor and between the rest of the semiconductor region and the insulating layer, and has side surfaces reaching the side oxide film. In the semiconductor device, the semiconductor region has a length of 2 xcexcm or more in the gate width direction.
Thus, it is possible to reduce the area ratio of part of the semiconductor region having a crystal strain to the entire semiconductor region. This suppresses the occurrence of crystal defects or abnormal diffusion of a dopant impurity in the semiconductor region. Therefore, in the semiconductor device of the present invention, the occurrence of source-drain leakage due to abnormal diffusion of the dopant impurity in the source and drain regions, source-substrate junction leakage or the like can be suppressed/prevented.
The percentage of the dimension of the bottom oxide film extending inwardly from the side surface of the trench with respect to the dimension of the semiconductor region in the gate width direction is preferably 15% or less.
Still another semiconductor device in accordance with the present invention includes: an insulating layer; first and second semiconductor regions formed on the insulating layer; a trench that surrounds the first and the second semiconductor regions and reaches the insulating layer; an isolation insulating film formed in the trench; a first FET including a first gate insulating film formed on the first semiconductor region, a first gate electrode formed on the first gate insulating film and first source/drain regions formed on both sides of the first gate electrode; a second FET including a second gate insulating film formed on the second semiconductor region, a second gate electrode formed on the second gate insulating film and second source/drain regions formed on both sides of the second gate electrode; a first oxide film formed by oxidizing a bottom part of the first semiconductor region and located over the entire interface between the rest of the first semiconductor region and the insulating layer; and a second oxide film formed by oxidizing a peripheral portion of a bottom part of the rest of the second semiconductor region and located under the peripheral portion of the rest of the second semiconductor region and between the rest of the second semiconductor region and the insulating layer.
According to the present invention, the semiconductor device includes a first oxide film formed by oxidizing a bottom part of the first semiconductor region and located over the entire interface between the rest of the first semiconductor region and the insulating layer. This suppresses the occurrence of a crystal strain in the first semiconductor region in the first FET. Therefore, there can be suppressed the occurrence of crystal defects or abnormal diffusion of a dopant impurity in the peripheral portion of the semiconductor region that is to serve as an active region.
The second semiconductor region preferably has a length of 2 xcexcm or more in the gate width direction.
Thus, also in the second FET, it is possible to reduce the area ratio of part of the second semiconductor region having a crystal strain to the entire second semiconductor region in the second semiconductor region. This suppresses the occurrence of crystal defects or abnormal diffusion of the dopant impurity in the second semiconductor region.
Each of the first and second gate electrodes may be part of a common linear conductive film.
The first and second gate electrodes may be arranged in parallel to each other.
A method for fabricating a semiconductor device in accordance with the present invention includes the steps of a) preparing a semiconductor substrate including an insulating layer and a semiconductor layer formed on the insulating layer; b) forming a mask on the semiconductor layer and then performing etching using the mask to form a trench for dividing the semiconductor layer into a plurality of semiconductor regions; and c) oxidizing side parts of the plurality of semiconductor regions which are exposed to the trench, wherein in the step b), the semiconductor layer is divided into a plurality of semiconductor regions so that an oxide film to be formed in the step c) is located over the entire interface between each said semiconductor region and the insulating layer and includes side surfaces that reach the trench.
In the fabrication method of the present invention, the semiconductor layer is divided into a plurality of semiconductor regions so that an oxide film to be formed in the step c) is located over the entire interface between each said semiconductor region and the insulating layer and includes side surfaces that reach the trench. This suppresses the occurrence of a crystal strain in each said semiconductor region. Accordingly, there can be achieved a semiconductor device in which the occurrence of a crystal strain or abnormal diffusion of a dopant impurity in a semiconductor region can be suppressed.
In the step b), the semiconductor layer is preferably divided into a plurality of semiconductor regions so that each said semiconductor region has a length of 0.5 xcexcm or less in the gate width direction.
Thus, the occurrence of a crystal strain in each said semiconductor region can be suppressed to a greater extent.
The inventive method may further includes the steps of: d) forming an isolation insulating film in the trench; e) forming a gate insulating film on each said semiconductor region and then a gate electrode on the gate insulating film; and f) forming source/drain regions on both sides of the gate electrode.